// implementation of a clock generator
module ClockGen(clk);
  output clk;
  reg clk;
  parameter half_cycle=5;
  parameter stop_time=500;

  initial
    begin: clock_loop
      clk=1;
      #5 clk=0; //begin with a negedge
      forever
        begin
          #half_cycle clk=0;
          #half_cycle clk=1;
        end
    end

  initial
    #stop_time disable clock_loop;
endmodule
